Integrated circuits are realized on a semiconductor substrate by disposing stacked layers of conducting patterns for interconnecting transistors and other circuit components. As the scale of integration increases, distances of separation both in the vertical and horizontal directions among interconnect lines become increasingly small. These technological advances in the fabrication technologies lead to a net increase of coupling capacitances between neighboring conducting lines belonging to metal levels or even to the same metal. These capacitances cannot be neglected in designing integrated circuits because of the influence they have on the operation of the circuits also in consideration of the ever increasing clock frequencies of electronic circuits.
Therefore, it is necessary to measure the coupling capacitances among neighboring lines such as between adjacent parallel lines or superimposed or even intersecting. Moreover, measuring these capacitances may provide a measure of the thickness of a dielectric layer that may be interposed between superimposed lines.
Capacitance measurement is useful also in DNA analysis. The paper by A. Bogliolo et al. “A Biosensor for Direct Detection of DNA Sequences Based on Capacitance Measurements”, Proc. of the 32th European Solid-State Device Research Conference, pp. 479-482, 24-26 Sep. 2002, showed that hybridization of self assembled monolayers (SAMs) of oligonucleotides probes of a DNA sensor causes a capacitance variation of the sensor. Therefore, hybridization of DNA probes may be detected by monitoring the capacitance variation of the sensor.
The so-called charge-based capacitive measurement (CBCM) technique is gaining importance for on chip interconnect capacitance measurements because of its accuracy and simplicity as discussed in D. Sylvester et al., “Investigation of Interconnect Capacitance Characterization Using Charge-Based Capacitive Measurement (CBCM) Technique and Three-Dimensional Simulation”, IEEE J. of Solid-State Circuits, Vol. 33, No. 3, 1998, pp. 449-453. Test structures based on this technique are disclosed in the U.S. Pat. No. 5,999,010 to the assignee Simplex Solution Inc. and in the French Patent Application No. 98-07788 (corresponding to U.S. Pat. No. 6,366,098) in the name of STMicroelectronics S.A. Moreover, the paper by A. Bogliolo et al. “Charge-based on chip measurement technique for the selective extraction of cross-coupling capacitances”, Proc. of 6th IEEE Workshop on Signal Propagation on Interconnects, pp. 75-77, 12-15 May 2002, discloses a simple test structure implementing a CBCM technique that allows a selective extraction of a cross-coupling capacitance between arbitrary on-chip interconnect lines.
A drawback of the circuits disclosed in the above mentioned documents is that they measure the total parasitic capacitance of an interconnect line, such that the coupling capacitance between two metal lines must be necessarily assessed by repeating the tests under different conditions for calculating the parasitic capacitances between the considered lines and ground. Moreover, the known circuits use at least two switched transistors connected between a node at the supply voltage and the virtual ground node of the circuit. Therefore, to prevent large short-circuit currents, they must be driven by non overlapping PWM signals.